An Autozeroing Floating-gate Second-order Section

We introduce the Autozeroing Floating-Gate Second-Order Section. We built this second-order lter where the corner frequency and Q are electronically tunable based on a classic lter topology and principles of OTA ampli ers. We built this second-order lter using three AFGAs| our oating-gate ampli er that sets its operating point by the interaction of hot-electron injection and electron-tunneling. We introduce the Autozeroing Second-Order Section (AutoSOS) in this paper. The second-order section is the primary element to build higher-order lters, both in continuoustime and switch-capacitor circuits. Figure 1 shows the autozeroing second-order section. This circuit is based on the Di 2 second-order section [3], which in turn is based on a canonical form for a second-order section as a high-gain ampli er with feedback. This circuit uses the autozeroing oating-gate ampli er (AFGA) that we invented previously [1, 2]. The AFGA does not require any clocking to eliminate o sets, as in switched-capacitor circuits [4], but utilizes an inherent combination of electron-tunneling and hot-electron{injection currents to eliminate the DC signal. This paper illustrates how to build higher-order lters from AFGAs, as well as proving the feasibility of circuits with multiple oating-gate devices. Using AFGAs as the core lter block merges many of the bene ts of switchedcapacitor [4], and transconductance-ampli er or OTA [3] lters. The AFGA-based lters can tuned electronically the corner frequencies over many orders of magnitude, as in transconductance-ampli ers. Because many of the AFGA's circuit properties|bandpass gain bandpass gain, linear range, and dynamic range|are set by ratios of capacitors, the AFGA-based lters utilize capacitor matching as is done in switched-capacitor lters. Also, the AFGA lters its o sets, 1=f noise without resorting to the chopper-stabilizing clocking schemes present in switched-capacitor [4] lters. We present data from circuits fabricated in a 2 m n-well Orbit CMOS process available through MOSIS. Typical operating values for Vtun were between 33V to 42V ; those for Vdd were 6V to 12V . We obtain similar data in the 1:2 m nwell Orbit CMOS process, but with typical operating values for Vtun between 26V and 31V . For processes with smaller line widths, the typical operating voltages will decrease due to the thinner gate oxide and higher substrate doping. 1. AUTOZEROING FLOATING-GATE AMPLIFIER Figure 2 shows the AFGA. The AFGA has four operVdd Vtun